| Maria Mendez Real |  |
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Date de l'exposé : 20 janvier 2017, 10h30-11h30, salle Petri/Turing
Spatial Isolation against Logical Cache-based Side-Channel Attacks on Multi/Many-Core Architectures
Logical Side-Channel Attacks (SCA) allow an attacker which has no physical access to the system to perform powerful attacks against sensitive operations including cryptographic implementations. The cache memory is a shared resource that several processing elements compete for. In this talk we will focus on SCA seeing the cache as the source of leakage. Indeed, when a victim and an attacker processes share a cache (level 1, or last level cache), the attacker is able to deduce sensitive information about the victim by monitoring its own performance, the victim execution time or memory access patterns, all influenced by the shared cache activity. For instance, the monitored information can be exploited in order to reveal a cryptographic key. Implementations in the litterature have proved these attacks a real threat. Recently these attacks have been extended to Network-on-Chip multi/many-core systems. These latter offer massive parallelism allowing a great number of applications to execute concurrently on the same physical resources. However, the great resource sharing introduces key security vulnerabilities. Sensitive applications sharing physical resources with potentially malicious applications can be attacked. Current solutions are not longer sufficient and need to be revisited or adapted to these recent technologies. In our research work, we propose to spatially isolate the execution of a sensitive application on a secure zone in order to prevent any cache sharing with this sensitive application. This generic system level countermeasure prevents attackers from analyzing the victim s cache activity. Consequently, logical cache-based SCA cannot longer be performed. During this talk, we will analyze different strategies for the deployment and management of the secure zones in multi/many-core architectures. These countermeasures have been implemented through a virtual prototyping tool and have been evaluated and compared in terms of induced performance overhead.
