| Paolo Maistri |  |
 |
Date de l'exposé : 2 décembre 2016, 10h30-11h30, salle Petri/Turing
Hardware Design of Error Detection Schemes for Symmetric Ciphers
Secure hardware implementations are often used to accelerate cryptographic implementations; however, designers are well aware that cost and performance are not their only goal. Attacks exploiting side channel leakage or faulty behaviour are a serious threat that do not always require expensive equipment to be carried out, and can affect both symmetric and public-key cryptosystems. Hardware implementations must hence adopt solutions in order to make these attacks harder. In this talk we will present a few schemes aiming at detecting faulty computations in symmetric ciphers, with a particular focus on the Advanced Encryption Standard. Two countermeasures will be primarily addressed: temporal redundancy based on a double-data rate computation scheme, and a parity-based error detection code automatically generated from the RTL structure of the design. Several experimental results will be provided in order to show the validity of the proposed approaches.
