Date de l'exposé : 26 juin 2015, 11h30-12h30, salle Petri/Turing
High performance Side Channel Analysis implementation : parallelization using multi-core CPU and GPUAlgorithms used in cryptography are mathematicaly sure, or are based on mathematical problem considered hard to be solved. Nevertheless when those algorithms are implemented on smart-card or other device, some leak can appear.
We will first present briefly some attacks which take avantage on those leakages. Then we will focus on the Side Channel Analysis, a non-invasive type of attack exploiting leakage such as power consumption or electromagnetic radiation. A classical estimation of the Pearson coefficient will be detailed. We will explain why parallel programming is essential to use all the computational power of multi-core CPU. Different implementations will be proposed in this way to compute the estimation of the Pearson coefficient. GPUs offer a good alternative to CPUs for lower cost. Unfortunately this it not for free. We have to redesign all implementation to deal with the model of GPGPU, the Single Instruction for Multiple Data. We will present the example of Pearson coefficient which is easily suitable to SIMD model. Then we will discuss about the difficulty to compute an other coefficient, the Spearman coefficient. Finally we will explain a suitable method to calculate this coefficient.