Date de l'exposé : 11 décembre 2015, 10h30-11h30, salle Petri/Turing
Hiding your Secrets: Dual-Rail Precharge Logic Styles on FPGAsDesigners of secure hardware are required to harden their implementations against physical threats, such as power analysis attacks. In particular, cryptographic hardware circuits are required to decorrelate their current consumption from the information inferred by processing (secret) data. A common technique to achieve this goal is the use of special logic styles that aim at equalizing the current consumption at each single processing step. However, since all hiding techniques like Dual-Rail Precharge (DRP) were originally developed for ASICs, the deployment of such countermeasures on FPGA devices with fixed and predefined logic structure (i.e., slices, LUTs, FFs, and routing switch boxes) poses a particular challenge. It is also well known that power equalization schemes are not capable to fully equalize the current consumption and hence secure a circuit just to a certain level.
In this talk I will give an overview about previous works, implementation techniques, and our recent research which has shown that a combination of DRP logic styles and other countermeasures (i.e. proper masking schemes) can result in circuits that are practically resistant against power analysis attacks on higher statistical orders.